Method for laminating and mounting semiconductor chip

ABSTRACT

A plurality of semiconductor chips each having an electrode surface are sequentially laminated and mounted. Initially, the electrode surfaces of the semiconductor chips are activated. Then, the semiconductor chips are positioned. Successively, the semiconductor chips are laminated and bonded by pressing such that a reaction layer is not formed or formation of the reaction layer is suppressed excessively. Finally, the semiconductor chips are entirely heated so as to form the reaction layer after lamination and bonding of all the semiconductor chips are completed.

BACKGROUND OF THE INVENTION

This invention broadly relates to a method for laminating and mounting asemiconductor chip. More specifically, this invention is directed to amethod for laminating and mounting a semiconductor chip in athree-dimensional manner.

In a technique for laminating and mounting the semiconductor chip of thetype described, when the semiconductor chips are directly laminated toeach other, a semiconductor chip with a small size is equipped on acircuit surface of the other semiconductor chip with a large size viaadhesives, and is sealed so as to obtain electrical connection by theuse of the known wire-bonding.

High-density mounting is realized by laminating the semiconductor chips.Under this circumstance, it is becoming increasingly important toassemble the semiconductor chips without giving damages against thecircuit surface in the cause of impact of the bonding.

To this end, it is necessary that the semiconductor chips to belaminated are sequentially reduced in sizes as a precondition forlamination. Consequently, the semiconductor chip must be thinlyprocessed in order to achieve high density of a semiconductor device.

Referring to now FIG. 1, description will be made about a related methodfor laminating and mounting a semiconductor chip. In short, laminatedsemiconductor chips are connected to each other by the wire-bonding in asemiconductor device illustrated in FIG. 1.

More specifically, a semiconductor chip 1 a and a semiconductor chip 1 bwith a size smaller than the semiconductor chip 1 a are laminated by Agpaste 13 on an interposer 12.

Further, the semiconductor chips 1 a and 1 b are electrically connectedby the use of wire-bonding wires 11, are sealed with mold resin 15, andthen are attached with an external terminals (solder bumps 14), thusconstituting the semiconductor device illustrated in FIG. 1.

However, thus-produced semiconductor device realizes the electricalconnection via the wire-bonding. In consequence, only semiconductorchips having different sizes to each other can be laminated in thiscase. Moreover, the semiconductor chips can not be equipped byface-down.

Accordingly, an additional region for the wire-bonding is necessary,thus being insufficient for the mounting with the high-density.

In addition, a large load is inevitably applied to the circuit surfaceof the semiconductor chip laminated at a lower stage in the cause of thewire-bonding for performing the electrical connection between thesemiconductor chip and the interposer after laminating the semiconductorchips. This may cause to destroy the semiconductor chip.

In the meantime, there is a method for laminating the semiconductorchips after assembling the semiconductor device suitable for thelamination without directly laminating the semiconductor chips asanother related method for laminating and mounting the semiconductorchips.

Referring to FIGS. 2A and 2B, description will be made about suchanother related method for laminating and mounting the semiconductorchips.

A semiconductor chip 1 is arranged on an interposer 12, and a solderbump 14 is formed thereon. Here, the arranged semiconductor chip 1 andinterposer 12 are thinly processed within the range of standoff of thesolder bump 14 for lamination.

After these semiconductor devices 1 and 3 are laminated and equippedwith a desired number, a reflow process is entirely carried out toconnect electrodes. Herein, it should be noted that the referencenumeral 16 represents flux.

However, use must be made at every semiconductor chips for laminatingthe interposer in such a method, thus being not capable of producing athin semiconductor device.

Further, although entire reflow is carried out during the lamination, aself-alignment process is also possible. Specifically, the laminationbecomes possible only when a relatively large solder bump for a pitchbetween 0.5 mm and 1 mm is used so as to eliminate or reduce variationof flatness or positioning accuracy.

Moreover, there is a method for laminating semiconductor chips with afine pitch as another related method for mounting semiconductor devices.

Referring to FIGS. 3A through 3D, description will be made about suchanother related method for mounting the semiconductor devices.

As illustrated in FIG. 3A, semiconductor chips 1 each having a circuitsurface 6 and a back surface 7 are positioned, and are bonded withsolder 4. Then, a semiconductor chip 1 to be subsequently laminated ispositioned to thereby to bond with the solder.

In such a condition, the entire reflow is not expected the effect of theself-alignment because of the fine pitch. Consequently, the solderbonding is inevitably carried out sequentially. Herein, it should benoted that the reference numeral 2 represents a penetration electrode,the reference numeral 3 represent a bump, and the reference numeral 5represents a solder bonding layer.

According to such a method, it is becoming important to enhancepositioning accuracy of the electrodes of the semiconductor device, tosufficiently examine composition of electrode material of thesemiconductor chip, and to further reduce thermal hysteresis duringlaminating and mounting.

However, it is difficult to miniaturize the semiconductor device in therelated lamination method. Further, it is also difficult to entirelybond by reflow after laminating the semiconductor chips with a desirednumber in case where the semiconductor chip with a fine electrode ismounted. Consequently, the semiconductor chips must be sequentiallylaminated, and must be bonded by solder.

In this event, heat, which is applied during bonding the solder severaltimes until the final lamination, is loaded for the bonding portionwhich is laminated initially. Thereby, the structures of the bondingportions are different between the first stage and the final stage.Further, reliability is lowered by heating repeatedly.

Taking such circumstances into consideration, electrode specification ofthe interposer must be changed at every laminations and layers,resulting in high cost.

SUMMARY OF THE INVENTION

It is therefore an object of this invention to provide a method forlaminating and mounting a semiconductor chip, which is capable ofmounting the semiconductor chip by entire heating reflow afterlamination in a method for laminating and mounting a semiconductor chipwith a fine electrode.

It is another object of this invention to provide a method forlaminating and mounting a semiconductor chip, which is capable ofmanufacturing the semiconductor chip with high uniformity andreliability at a bonding portion.

According to this invention, a plurality of semiconductor chips eachhaving an electrode surface are sequentially laminated and mounted.

Initially, the electrode surfaces of the semiconductor chips, which arearranged in opposition to each other, are activated.

Then, the semiconductor chips are positioned.

Successively, the semiconductor chips are laminated and bonded bypressing such that a reaction layer is not formed or formation of thereaction layer is suppressed excessively.

Finally, the semiconductor chips are entirely heated so as to form thereaction layer after lamination and bonding of all the semiconductorchips are completed.

Under this circumstance, supersonic wave may be applied in addition tothe pressing in the laminating and bonding step.

Further, a bump is formed on the semiconductor chip, and the electrodesurface includes solder formed on the bump.

Alternatively, a bump is formed on the semiconductor chip, and theelectrode surface includes solder containing an active component formedby electroless plating.

In this event, the reaction layer comprises a bonding layer made ofsolder. The reaction layer may be uniformly formed between thesemiconductor chips.

The activating step is preferably carried out in order to remove anorganic substance on the electrode surface.

Further, the pressing step is desirably carried out such that thebonding is performed via interatomic force by approaching the activatedelectrode surface to an interatomic distance.

The activating step may be carried out by an atomic beam of inactive gasexcited by plasma.

Alternatively the activating step may be carried out by irradiatingradical fluorine or by sputtering.

Instead, the activating step may be carried out by thermally processingin reduction gas.

Specifically, the method according to this invention does not adopt sucha method that the semiconductor chips are heated for each one-stagelamination, and are sequentially bonded.

The method of this invention adopts such a method that the lamination iscarried out without heating instead of the temporary connection due toadhesion such as flux in the multiple lamination mounting of thesemiconductor chips. In this condition, the heating and the solderbonding are completed after all lamination steps are finished.

Thus, the lamination is performed by the bonding without the heating,and the bonding is completed by the entire reflow. Thereby, the reactionlayers can be formed in the same structure between the first stage ofbonding portion and the final stage of bonding portion.

To this end, the thermal load applied to the bonding portion and thesemiconductor chip becomes uniform, thus obtaining equal bondingstrength. Consequently, it can be avoided that the reliability of thebonding portion is different in dependency upon the reliability ofkeeping under the high temperature. Further, the semiconductor chiphaving the electrode with the fine pitch can be laminated with highaccuracy.

More specifically, heating is not carried out during temporary bondingThereby, the lamination can be performed without the reaction layer.Instead, the lamination may be carried out such that the formation ofthe reaction layer is suppressed excessively. As a result, the uniformreaction layer is formed for each lamination and layer by entirelyheating during bonding, thus being stable in structure.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a cross sectional view showing a related technique forlaminating and mounting semiconductor chips;

FIGS. 2A and 2B are cross sectional views showing another relatedtechnique for laminating and mounting semiconductor chips;

FIGS. 3A through 3D are cross sectional views showing still anotherrelated technique for laminating and mounting semiconductor chips;

FIGS. 4A through 4D are cross sectional views showing a method forlaminating and mounting semiconductor chips according to an embodimentof this invention; and

FIG. 5 is a flow chart showing a method for laminating and mountingsemiconductor chips according to an embodiment of this invention.

DESCRIPTION OF PREFERRED EMBODIMENTS

Referring to FIGS. 4A through 4D and FIG. 5, description will behereinafter made about a production method according to an embodiment ofthis invention.

In the flowchart illustrated in FIG. 5, a lamination process of asemiconductor chip is largely divided into a lamination temporarybonding step 20 and a lamination heating bonding step 21.

In this condition, the lamination temporary bonding step includes asurface activation step 201, a positioning step 202, and apressing/equipping step 203. On the other hand, the laminationheating-bonding step comprises a heating bonding step 204.

As illustrated in FIG. 4, bumps 3 are formed on a circuit surface 6 anda back surface 7 of a semiconductor chip 1, and solder 4 is supplied onthe bump 3. Herein, it should be noted that the reference numeral 2indicates a penetration electrode.

For such a semiconductor chip 1, sputtering is carried out underreduction atmosphere, and alternatively, variety types of gases areintroduced. Under this condition, an atomic beam excited by plasma isirradiated, so that organic substance on the surface of the solder 4formed on the bump 3 is removed and activated (step 201).

The similar process is carried out for the semiconductor chip 1 to belaminated. Further, positioning is conducted in the reduction atmospheresuch that the surface of the semiconductor chip 1 activated for thesurface is not contaminated again as needed (step 202). Thereafter,pressing is carried out (step 203).

By pressing, the activated surface layer is close to an interatomicdistance to thereby realize the bonding by interatomic force. Suchbonding is carried out without heating. Thereby, a reaction layer (asolder bonding layer 5) is not formed. Alternatively, the formation ofthe reaction layer may be suppressed excessively. Through this step, thelamination can be performed by such temporary bonding that the reactionlayer 5 is not formed.

After a desired number of semiconductor chips are laminated in thelamination temporary bonding step 20, the lamination mounting process iscompleted by heating up to such temperature to be bonded by solder (step204).

By adopting this method, a washing step after bonding becomesunnecessary because the temporary attachment due to the adhesion of theflux is not carried out.

Further, heating is entirely performed after laminating a desired numberof semiconductor chips without heating and bonding during lamination.Thereby, the bonding portion with high reliability having a uniformreaction layer is advantageously formed for each lamination and layer.Thereafter, the semiconductor chip is sealed with resin as needed, andis attached with the external terminal.

In the aforementioned embodiment, the surface activation step and thelamination temporary bonding step may not be carried out in thereduction atmosphere.

Alternatively, the surface activation may be performed by irradiating anatomic beam of inactive gas excited by plasma or radical fluorine or theother activated gas excited by plasma or the other gases. Instead, itmay be performed by the sputtering method or by a thermal process in thereduction gas.

Further, the lamination temporary bonding may be carried out in thereduction atmosphere in the air on the condition that the surfaceactivation is kept, or under inactivation atmosphere.

Moreover, the lamination temporary bonding due to pressing after thesurface activation may be carried out by applying supersonic wave inaddition to pressing.

In this case, although the solder 4 is supplied onto the bump 3, thesolder may be supplied by the use of the electroless plating, and thesolder containing component for activating the surface therein may beused.

The surface is activated by a reduction operation of phosphorouscontained in the electroless plating, thus substituting or aiding thesurface activation step. Herein, active component contained in thesolder may be not phosphorous.

Further, the solder 4 may not be supplied onto the bump 3. Copper, gold,aluminum, and a variety of combinations of metal materials serving asthe bump can be used by adjusting the method for the activating thesurface and the reduction environment of atmosphere for the laminationaccording to the lamination method of this invention.

EXAMPLE First Example

Referring to FIG. 4, description will be made about a first example ofthis invention.

The bumps 3 on the circuit surface 6 and the back surface 7 are formedby copper, and tin is supplied on the bumps 3 made of copper with0.2˜0.5 μm as the solder 4.

The semiconductor chips 1 to be laminated are activated with thesurface, and are positioned to each other. Then, they are arranged in anapparatus with function for pressing and equipping, and are exposed in avacuum state of about 1×10E-3˜1×10E-5 pa. Thereafter, argon gas isintroduced therein so as to generate plasma, and argon atoms areirradiated towards the surface of the bump for 5 minutes.

In this event, irradiation time depends upon an etching rate of materialsupplied as the bump or the solder, and is selected within the rangebetween 1 minute and 20 minutes. Thereafter, the semiconductor chips arepositioned to each other in such reduction atmosphere, and then arepressed so as to plastically deform such that the bonding surfaces ofthe bumps are joined to each other.

The temporary bonding is completed for the bump with the activatedbonding surface via the aforementioned process. Thus, the laminationbody, which is formed by temporally bonding sequentially, is heated upto 200° C., and the final bonding is completed by diffusing tin.

In the first example, the argon atomic beam is used in vacuum toactivate the surface. Alternatively, gas excited by plasma in the airmay be used. Further, although the pressing and temporary bonding afterthe surface activation is carried out in the air, it may be performed inthe air introduced with gas such as nitrogen and argon,

Second Example

Referring to FIG. 4, description will be made about a second example ofthis invention.

The bumps 3 on the circuit surface 6 is formed by gold while the bump 3on the back surface 7 is formed by copper.

The semiconductor chips 1 to be laminated are activated with thesurface, and are positioned to each other. Then, they are arranged in anapparatus with function for pressing and equipping, and are exposed in avacuum state of about 1×10E-3˜1×10E-5 pa. Thereafter, argon gas isintroduced therein so as to generate plasma, and argon atoms areirradiated towards the surface of the bump for 10 minutes.

Thereafter, the semiconductor chips are positioned to each other in suchreduction atmosphere, and then are pressed so as to plastically deformsuch that the bonding surfaces of the bumps are joined to each other.

The temporary bonding is completed for the bump with the activatedbonding surface via the aforementioned process. Thus, the laminationbody, which is formed by temporally bonding sequentially, is heated upto 250° C., and the final bonding is completed by alternately diffusinggold and copper.

In this case, although the heating temperature is set to 250° C., theheating may be carried out under higher temperature such that thesemiconductor chip does not become defective. Moreover, the material ofthe bump may be changes suitably, and the metal material can be combinedfreely.

While this invention has thus far been disclosed in conjunction withseveral embodiments thereof, it will be readily possible for thoseskilled in the art to put this invention into practice in various othermanners.

What is claimed is:
 1. A method for sequentially laminating and mountinga plurality of semiconductor chips each having an electrode surface,comprising the steps of: activating the electrode surfaces of thesemiconductor chips which are arranged in opposition to each other;positioning the semiconductor chips; laminating and bonding thesemiconductor chips by pressing such that a reaction layer is not formedor formation of the reaction layer is suppressed; entirely heating thesemiconductor chips so as to form the reaction layer after laminationand bonding of all the semiconductor chips are completed; wherein thereaction layer is uniformly formed between the semiconductor chips; andwherein the pressing step is carried out such that the bonding isperformed via interatomic force by approaching the activated electrodesurface to an interatomic distance.
 2. A method as claimed in claim 1,wherein: supersonic wave is applied in addition to the pressing in thelaminating and bonding step.
 3. A method as claimed in claim 1, wherein:a bump is formed on the semiconductor chip, and the electrode surfaceincludes solder formed on the bump.
 4. A method as claimed in claim 1,wherein: a bump is formed on the semiconductor chip, and the electrodesurface includes solder containing an active component formed byelectroless plating.
 5. A method as claimed in claim 1, wherein: thereaction layer comprises a bonding layer made of solder.
 6. A method asclaimed in claim 1, wherein: the activating step is carried out in orderto remove an organic substance on the electrode surface.
 7. A method asclaimed in claim 1, wherein: the activating step is carried out by anatomic beam of inactive gas excited by plasma.
 8. A method as claimed inclaim 1, wherein: the activating step is carried out by irradiatingradical fluorine.
 9. A method as claimed in claim 1, wherein: theactivating step is carried out by sputtering.
 10. A method as claimed inclaim 1, wherein: the activating step is carried out by thermallyprocessing in reduction gas.
 11. The method as claimed in claim 1,wherein the electrode surface of each of said plural semiconductor chipsis vertically aligned with one another.
 12. A method of mounting pluralsubstantially identical semiconductor chips, comprising the step of:placing solder on each opposing bump of adjacent semiconductor chips;activating a surface of the solder; directly contacting at least twoopposing bumps of said adjacent semiconductor chips with each other;pressing said adjacent semiconductor chips together to bond them withoutheating; then heating said plural semiconductor chips after all of theplural semiconductor chips to be heated have been pressed together; areaction layer is uniformly formed between the semiconductor chips; andwherein the pressing step is carried out such that the bonding isperformed via interatomic force by approaching the activated surface ofthe solder to an interatomic distance.
 13. The method as claimed inclaim 12, wherein said activating step comprises irradiating an atomicbeam excited by plasma.
 14. The method as claimed in claim 12, whereinsaid activating step and said pressing step are performed in a reductionatmosphere.
 15. The method as claimed in claim 12, wherein said placingsolder step comprises electroless plating said bumps.
 16. A method ofmounting plural substantially identical semiconductor chips, comprisingthe steps of: activating a surface of plural metal bumps on saidsemiconductor chips; directly contacting at least two opposing bumps ofsaid adjacent semiconductor chips to be each other; pressing saidadjacent semiconductor chips together to bond them without heating; thenheating said plural semiconductor chips after all of the pluralsemiconductor chips to be heated have been pressed together; a reactionlayer is uniformly formed between the semiconductor chips; and whereinthe pressing step is carried out such that the bonding is performed viainteratomic force by approaching the activated surface of the pluralmetal bumps to an interatomic distance.
 17. The method as claimed inclaim 16, wherein the plural metal bumps are one of copper, gold andaluminum.